搜索资源列表
FSM
- FPGA学习资料，新手入门资料,VERILOG- Micron SDRAM DDR2 Simulation model Verilog
ddr
- DDR2内存条在FPGA中的应用,包括内部结构，时序操作和注意事项。-about DDR2 APLLICATION IN FPGA，includ inner instraction timequist and attend.
npi_write
- 从FPGA向DDR2写入数据。采用NPI接口。单字写入。是用Verilog HDL 写的-Write data from the FPGA to DDR2. Using NPI Interface. The word is written. Is written using Verilog HDL
DDR2_40
- 红色飓风四代开发版读取内存DDR2的开发例程，对于fpga开发者应该会有一定帮助的，我分享上来 -The red hurricane development version of four generations read the development of memory DDR2 routine fpga developers should have some help, I share up
fpga_hb_emi_ddr2_ciii_sopcb
- fpga 视频开发必备的 DDR2操作。官方代码。可以参考参考。-The fpga development essential DDR2 video operations. The official code. You can refer to
dual
- DDR2双内存切换程序部分代码,用于VHDL的FPGA开发-DDR2 dual memory switching part of the program code for VHDL-FPGA development
ddr2_v5
- 基于FPGA v5的ddr2-sdram控制器的设计verilog-Based on FPGA v5 of ddr2-sdram controller design verilog
adr_cntrl_timing
- 对于得ddr2开发重要的文档，可以用fpga完成设计实现。-For the development of important documents have ddr2 can be used to complete the design fpga implementation.
DDR2_Control
- FPGA SIGA S16 DDR2 驱动-FPGA SIGA S16 DDR2 DRIVER
DDR2_Control
- 本文档以Siga-S16 Spartan 6的FPGA开发板为例，为大家介绍用MIG工具生成DDR2控制器，并用ChipScope调试DDR2读写的方法。 -This document in the FPGA development board Siga-S16 Spartan 6 as an example, to introduce the formation of DDR2 controller with the MIG tool, and use the debug method of
PCI_Express_AD1_1
- pci-e高速ad高速采集，应用ddr2，fpga逻辑，verilog语言-pci-e ad-speed high-speed acquisition, application ddr2, fpga logic, verilog language
cdanpianji
- 红色飓风四代 altera DDR2 FPGA 开发 -FPGA development DDR2
Xilinx_DDR2_IP_TEST
- 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH，无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed descr iption. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
DDR2_XILINX
- xilinx FPGA设计需要的DDR2文件，可以应用于实际设计中-xilinx FPGA design needs DDR2 files that can be applied to the actual design
ddr2_controller
- A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
mt9d112_ddr2
- 镁光MT9基于FPGA图像采集模块，该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory
OV7670_DDR2_VGA
- 在FPGA下的视频采集显示，采用纯Verilog编写，其中包括有OV7670摄像头，高速存储器DDR2，ADV芯片的VGA。-In FPGA video capture display, using pure Verilog prepared, which includes OV7670 camera, high-speed memory DDR2, ADV chip VGA.
DDR2_Control
- 本源码是用FPGA控制DDR2芯片的vhdl源码，并使用了modelsim仿真软件测试代码-The source is the use of FPGA control DDR2 chip vhdl source, and the use of modelsim simulation software test code